TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

ABSTRACT

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 13/647,474, filed Oct. 9, 2012, the entire disclosure of which is hereby incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The invention relates to extended wafer-level ball grid array (eWLB) packaging technologies, and more particularly, to a two-sided-access eWLB package a TSA eWLB assembly, and a method.

BACKGROUND OF THE INVENTION

Extended, or embedded, wafer-level ball grid array (eWLB) packages are used to extend the size of a WLB package beyond the area of the integrated circuit (IC) die in order to provide it with a higher ball count and greater fan out for making electrical interconnections between the pads of the IC die and external electrical circuitry. After the IC dies have been fabricated on a semiconductor wafer, they are singulated into individual dies. The individual dies are then reconstituted on an artificial wafer, which typically comprises a piece of tape on which the dies are positioned front face down and a polymer molding material that encapsulates the dies. It should be noted that the dies that are reconstituted on the artificial wafer may be the same types of dies that were singulated from the same wafer or they may be different types of dies that were singulated from different types of wafers.

After the polymer molding material has been cured to form a mold about the dies, the tape is removed to expose the front side of the wafer, which is the side of the artificial wafer that is co-planar with the front faces of the dies. Wafer-level processes are then used to deposit and pattern layers of dielectric material and metal on the front side of the artificial wafer to form conductive traces. First ends of the conductive traces are in contact with the pads of the dies. Second ends of the conductive traces fan out away from the respective dies. Solder balls are then deposited at particular locations on the front side of the artificial wafer in contact with the second ends of the conductive traces, thereby establishing electrical interconnections between the solder balls and the pads of the respective dies. The artificial wafer is then sawed to singulate the individual eWLB packages from one another. Each singulated eWLB package contains at least one die, but may contain more than one die. In cases where the eWLB package contains more than one die, the dies may of the same type or different types.

After the eWLB packages have been singulated, an eWLB package is typically mounted on a printed circuit board (PCBs) on which other IC packages and/or other electrical components are also mounted. The eWLB package is placed on the PCB such that the solder balls of the eWLB package are in contact with electrical contacts of the PCB. The side of the eWLB package on which the solder balls are disposed is typically referred to as the front side of the package, whereas the opposite side of the eWLB package is typically referred to as the rear side of the package. A solder reflow process is then performed to permanently bond the solder balls of the eWLB package to the respective electrical contacts of the PCB. In this way, the pads of the die(s) of the eWLB package are electrically interconnected with the electrical contacts of the PCB.

In eWLB packages, any electrical wiring that needs to be made inside of the mold is made from the front side of the eWLB package. In some cases, however, electrical contact pads of the die are located on the rear face of the die, or on both the front and rear faces of the die. For example, most optoelectronic dies such as light emitting diode (LED) dies, photodiode dies and vertical cavity surface emitting laser diode (VCSEL) dies have electrical contact pads on their front and rear faces. Forming the electrical wiring that is needed to make the electrical interconnections between the solder balls of the eWLB package and electrical contact pads located inside of the mold on the rear faces of the dies can be difficult due to the fact that these contact pads are inside of the mold.

A variety of solutions to this problem have been proposed, some of which are disclosed in U.S. Pat. No. 7,048,450, which is assigned to the assignee of the present application and which is incorporated herein by reference. Such solutions typically involve creating a thru-mold via (TMV) that extends from the front side of the eWLB package to the rear side of the package and then connecting the TMV to the contact pad(s) disposed on the rear face of the die with a bond wire or a metal bridge. While such solutions work satisfactorily, they are relatively difficult to implement. Also, the use of bond wires and the like is inconsistent with one of the benefits of eWLB technology, which is that it avoids the use of bond wires and uses wafer-level processes to form the interconnections between the solder balls and the contact pads of the die.

A need exists for an eWLB package and method that allow electrical connections to be more easily made to the rear faces of the dies.

SUMMARY OF THE INVENTION

The invention is directed to a TSA eWLB package, a TSA eWLB assembly, and a method. The TSA eWLB package comprises a mold having a front side and a rear side, a redistribution layer disposed on front side of the mold, at least a first IC die disposed inside of the mold such that a front face of the first IC die is in contact with a redistribution layer disposed on a front side of the mold, a first metal stamp disposed on a rear face of the first IC die such that a portion of the metal stamp is exposed through the rear side of the mold, and at least a first solder ball disposed on the exposed portion of the metal stamp.

The TSA eWLB assembly comprises a TSA sWLB package mounted rear-side down on an upper surface of a PCB such that at least a first solder ball of the TSA eWLB package is in contact with the one of a plurality of electrical contacts disposed on the upper surface of the PCB.

The method comprises providing a TSA eWLB package and mounting the TSA eWLB package rear-side down on an upper surface of a PCB such that at least a first solder ball of the TSA eWLB package is in contact with a respective one of a plurality of electrical contacts disposed on the upper surface of the PCB.

These and other features and advantages of the invention will become apparent from the following description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1E illustrate an exemplary embodiment of additional wafer-level process steps that are performed on the original IC die wafer that is used for fabricating IC dies that will subsequently be used (i.e., reconstituted) in artificial wafers of TSA eWLB packages.

FIGS. 2A-2E illustrate an exemplary embodiment of process steps that use IC dies created during the process steps shown in FIGS. 1A-1E to fabricate individual TSA eWLB packages.

FIG. 3 illustrates a side plan view of a TSA eWLB assembly comprising a TSA eWLB package formed by the process steps shown in FIGS. 2A-2E mounted on a PCB.

FIG. 4 illustrates a side plan view of a TSA eWLB assembly shown in FIG. 3, except that a refractive, Fresnel or holographic optical element (e.g., a lens) is formed in the dielectric layers of the redistribution layer above die.

FIG. 5 illustrates a side plan view of the TSA eWLB assembly shown in FIG. 3 with a cap secured to the upper surface of the TSA eWLB package.

FIG. 6 illustrates a side plan view of a TSA eWLB assembly in accordance with another illustrative embodiment comprising a TSA eWLB package mounted on a PCB.

FIGS. 7A-7E illustrate another illustrative embodiment of additional wafer-level process steps that are performed on the original IC die wafer to obtain IC dies that will subsequently be used (i.e., reconstituted) in TSA eWLB artificial wafers.

FIG. 8 illustrates a side plan view of a TSA eWLB assembly in accordance with another illustrative embodiment comprising a stack of TSA eWLB packages mounted on a PCB.

FIG. 9 illustrates a side plan view of a TSA eWLB assembly in accordance with another illustrative embodiment comprising a stack of TSA eWLB packages mounted on a PCB.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

In accordance with the invention, a two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die. Illustrative or exemplary embodiments of the TSA eWLB package and method will now be described with reference to the figures, in which like reference numerals are used to reference like elements, features or components. It should be noted that elements, features or components in the figures are not necessarily drawn to scale.

FIGS. 1A-1E illustrate additional wafer-level process steps that are performed on the original IC die wafer that is used for fabricating IC dies that will subsequently be used (i.e., reconstituted) in artificial wafers of TSA eWLB packages. After the IC dies have been fabricated in the original IC die wafer, but before the wafer has been sawed to singulate the IC dies, the process steps shown in FIGS. 1A-1E are performed. With reference to FIG. 1A, a metallization process is performed to form a metal layer 101 on a rear side 100 a of an original IC die wafer 100. With reference to FIG. 1B, a coating layer (e.g., a layer of photoresist) 102 is formed on top of the metal layer 101. With reference to FIG. 1C, the coating layer 102 is then patterned by, for example, using standard photolithographic techniques to mask certain areas of the coating layer 102 while other areas of the coating layer are exposed to ultraviolet (UV) radiation and then chemically etching away the exposed regions of the coating layer 102. When the exposed areas of the coating layer 102 are etched away, areas of the metal layer 101 are exposed. Other techniques may be used to pattern the coating layer 102, such as, for example, dry etching techniques.

With reference to FIG. 1D, after the coating layer 102 has been patterned, metal stamps 103 are formed on top of the exposed areas of the metal layer 101. The metal stamps may 103 are typically formed through a galvanic growth process during which the stamps 103 are galvanically grown on top of the exposed areas of the metal layer 101. The metal stamps 103 may be copper stamps, for example, although other metals may instead be used for this purpose. With reference to FIG. 1E, the remaining portions of the coating layer 102 are then removed by, for example, exposing the patterned coating layer 102 to UV radiation and then chemically etching it away. This leaves the free-standing metal stamps 103 on top of the metal layer 101. The wafer 100 having the metal layer 101 and the metal stamps 103 thereon is then singulated to produce individual IC dies 110, each of which has a respective metal stamp 103 on its rear face.

After the individual IC dies 110 have been singulated, the process of fabricating the TSA eWLB package is performed, as will now be described with reference to FIGS. 2A-2D. With reference to FIG. 2A, two different types of IC dies 110 and 111 are placed on a wafer-shaped piece of tape 112 with their front faces 110 a and 111 a, respectively, in contact with the upper surface 112 a of the piece of tape 112 that contains a layer of adhesive material (not shown). Both types of the IC dies 110 and 111 have the metal stamps 103 disposed on their rear faces 110 b and 111 b, respectively. The IC dies 110 having the stamps 103 on them were made by the process described above with reference to FIGS. 1A-1E. The IC dies 111 with the stamps 103 on them, while of a different type than the IC dies 110, were also made by the process described above with reference to FIGS. 1A-1E.

With reference to FIG. 2B, a polymer mold material 114 is then deposited over the IC dies 110, 111 such that the IC dies 110, 111, their respective stamps 103, and the upper surface 112 a of the tape 112 are encapsulated in the polymer mold material 114. The polymer mold material 114 is then cured to form a hardened mold 115 having a front side 115 a and a rear side 115 b. The piece of tape 112, the mold 115, the dies 110, 111, and their respective stamps 103 together comprise the artificial wafer 120. As can be seen in FIG. 2B, because the IC dies 110 and 111 are of different types, the distances between their front faces 110 a and 111 a, respectively, and the upper surfaces 103 a of the stamps 103 typically will not necessarily be equal.

With reference to FIG. 2C, a grinding process is performed on the rear side 115 b of the mold 115 to reduce the thickness of the mold 115 to the point that all of the metal stamps 103 are exposed through the rear side 115 b of the mold 115. Thus, the rear faces 110 b and 111 b of the dies 110 and 111, respectively, are now accessible via the respective metal stamps 103 through openings formed in the rear side 115 a of the mold 115.

As shown in FIG. 2D, the piece of tape 112 is then removed to expose the front faces 110 a and 111 a of the IC dies 110 and 111, respectively, thereby making the front faces 110 a and 111 a of the dies 110 and 111, respectively, accessible through openings formed in the front side 115 a of the mold 115.

After the wafer-level processing steps shown in FIGS. 2A-2D have been performed, additional wafer-level processing steps are performed to make electrical connections to electrical contact pads (not shown) disposed on the front faces 110 a, 111 a and rear faces 110 b, 111 b of the dies 110, 111, respectively, as will now be described with reference to FIG. 2E.

With reference to FIG. 2E, a redistribution layer 121 is built up on the front side 120 a of the artificial wafer 120. The redistribution layer 121 comprises layers of metal and layers of dielectric material that are patterned to form predetermined patterns of electrical traces 122. TMVs 123 are formed in the wafer 120 that extend through the mold 115 from the front side 115 a to the rear side 115 b of the mold 115. The TMVs 123 are formed by drilling holes in the mold 115 and then filling the holes with an electrically-conductive material. Some of the electrically conductive traces 122 have first ends that are connected to one of the TMVs 123 and second ends that are connected to electrical contact pads 124 disposed on the front faces 110 a, 111 a of the dies 110, 111, respectively.

On the rear side 120 b of the wafer 120, solder balls 127 are deposited on the TMVs 123 and on the metal stamps 103. Although the solder balls 127 are shown as being spherical in shape, the solder balls 127 are not necessarily spherical in shape and may have any shape. The term “solder ball,” as that term is used herein, is intended to denote a small amount of solder having any shape that allows it to provide the necessary electrical connection. Once all of the processing steps shown in FIGS. 2A-2E have been performed, the wafer 120 is singulated at the locations represented by the dashed lines 131.

FIG. 3 illustrates a side plan view of a TSA eWLB assembly comprising a TSA eWLB package 130 mounted on a PCB 140. The TSA eWLB package 130 is obtained by singulating the wafer 120 shown in FIG. 2E at the locations represented by the dashed lines 131. After the singulation process has been performed, the TSA eWLB package 130 is mounted rear side down on the PCB 140 such that the solder balls 127 are in contact with electrical contacts 141 disposed on the upper surface of the PCB 140. The contact pads 124 disposed on the front faces 110 a, 111 a of the dies 110, 111, respectively, are electrically connected by the electrical traces 122 to the TMVs 123, which are connected to electrical contacts 141 of the PCB 140 by the respective solder balls 127. Any contact pads (not shown) that are disposed on the rear faces 110 b, 111 b of the dies 110, 111, respectively, are electrically connected to electrical contacts 141 of the PCB 140 by the respective metal stamps 103 and the respective solder balls 127.

It can be seen from FIG. 3 that the configuration of the TSA eWLB package 130 allows the front faces 110 a, 111 a and rear faces 110 b, 111 b of the IC dies 110, 111, respectively, to be easily accessed without the need for using bond wires or the like to make electrical connections within the mold 115. Therefore, regardless of whether the contact pads of the dies 110, 111 are on the front faces 110 a, 111 a or the rear faces 110 b, 111 b, wafer-level processes can be used during the process of fabricating the TSA eWLB dies to make the necessary connections between the contact pads and the solder balls.

The invention is particularly well suited for making TSA eWLB packages that include at least one optoelectronic die, such as, for example, an LED, a VCSEL or a photodiode, due to the fact that such dies often have at least one electrical contact pad on their rear faces. For example, the dies 110 and 111 may correspond to, respectively: a photodiode die and a transimpedance (TIA)-post amplifier die; a VCSEL die and a VCSEL driver die; an LED die and an LED driver die; a VCSEL die and a photodiode die; and first and second LED dies. It should also be noted that in cases where the metal stamps 103 are not used for making electrical contact with contact pads of the dies, they can be used as heat dissipation devices for dissipating heat from the respective dies down into heat dissipation devices (not shown) disposed on the PCB.

FIG. 4 illustrates a side plan view of a TSA eWLB assembly shown in FIG. 3, except that a refractive, Fresnel or holographic optical element (e.g., a lens) 150 is formed in the dielectric layers of the redistribution layer 121 above die 110. In accordance with this illustrative embodiment, the die 110 is either a light source, such as a VCSEL or an LED, or a light receiver, such as a photodiode. The die 111 is either a driver die or a receiver IC die, depending on whether die 110 is a light source or a light receiver.

FIG. 5 illustrates a side plan view of the TSA eWLB assembly shown in FIG. 3 with a cap 160 secured to the upper surface 130 a of the TSA eWLB package 130. The cap 160 is made up of a plastic mold 161 having first and second tapered optical pathways 162 and 163 formed in it. The plastic mold 161 may be made of the same material that is used to make the mold 115 of the TSA eWLB package 130. The tapered optical pathways 162 and 163 are coated with a reflective material, such as metal, for example. In accordance with this example, die 110 is a light-emitting die such as a VCSEL or an LED and die 111 is a light-receiving die such as a photodiode. Light emitted by die 110 is directed by tapered optical pathway 162 in the direction indicated by arrow 165. Tapered optical pathway 163 directs light in the direction indicated by arrow 166 onto die 111. The emitting and receiving far fields are controlled by choosing the tapering angles and lengths of the tapered optical pathways 162 and 163. Light rays emitted by the light-emitting die 110 are reflected by the inner walls of the tapered optical pathway 162 such that the far field angle of emission is reduced. On the receiving side, only light rays that fall into the opening of the tapered optical pathway 163 will be incident on the light receiving die 111. Therefore, the far field angle of reception is reduced.

FIG. 6 a side plan view of a TSA eWLB assembly comprising a TSA eWLB package 170 mounted on a PCB 180. The TSA eWLB package 170 has first and second IC dies 190 and 210 and is made by the process described above with reference to FIGS. 1A-2E. The TSA eWLB package 170 is then mounted on the PCB 180 in the same manner described above with reference to FIG. 3. The IC dies 190 and 210 may be any types of IC dies, but for illustrative purposes, it will be assumed that the IC dies 190 and 210 are a non-silicon die and a silicon die, respectively.

In accordance with this illustrative embodiment, all electrical connections that are made to the front face 210 a of the silicon die 210 are made by thru-silicon vias (TSVs) 211 rather than by TMVs. The TSVs 211 are connected on first ends to respective solder balls 127 and on second ends to respective electrical traces 122, which are connected to respective electrical contact pads 124 disposed on the front face 210 a of the die 210. Electrical connections to electrical contact pads (not shown) disposed on the rear face 210 b of the dies 190 and 210 are made through contact between the stamps 103 and the respective solder balls 127.

The TSVs 211 may be formed during the process of fabricating the original IC die wafer 100 (FIG. 1A) or they may be formed at a later time, such as during the fabrication of the artificial wafer 120 (FIGS. 2B-2E). Typically, a process known as reactive ion etching (RIE) will be used to form the TSVs 211. Because RIE is a process that is typically performed at the wafer level with very high precision, the locations and sizes of the TSVs 211 can be carefully controlled. Typically, the bores of the TSVs 211 are filled with a metal material through a galvanic growth process similar to the process that is used to grow the stamps 103. Creating the TSVs 211 is often an easier process than creating TMVs in the molds 115 (FIG. 3).

FIGS. 7A-7E illustrate another illustrative embodiment of additional wafer-level process steps that are performed on the original IC die wafer to obtain IC dies that will subsequently be used (i.e., reconstituted) in TSA eWLB artificial wafers. In other words, after the IC dies have been fabricated in the original IC die wafer, but before the wafer has been sawed to singulate the IC dies, the process steps shown in FIGS. 7A-7E are performed.

With reference to FIG. 7A, RIE and galvanic growth processes are performed on the original IC die wafer 240 to form TSVs 241 at selected locations in the wafer 240. With reference to FIG. 7B, a thin layer of silicon oxide 242 is formed on an upper surface 240 a of the wafer 240. With reference to FIG. 7C, the silicon oxide layer 242 is then patterned by using, for example, standard photolithographic techniques to mask certain areas of the silicon oxide layer 242 while exposing the unmasked areas of layer 242 to UV radiation, and then chemically etching away the exposed areas of the layer 242. The locations where the layer 242 has been etched away correspond to areas where metal stamps and metal TSV contacts will subsequently be formed. A layer of copper 243 is then evaporated onto the remaining portions of layer 242 and exposed portions of the upper surface 240 a of the wafer 240.

With reference to FIG. 7D, a film layer 245 is formed on top of the copper layer 243 and then openings are formed in it by using lithographic techniques such as those described above with reference to FIG. 7C. At the locations where openings have been formed in the film layer 245, metal stamps 103 and metal TSV contacts 246 are galvanically grown on top of the copper layer 243.

With reference to FIG. 7E, the remaining portions of the film layer 245 and the copper layer 243 are removed, leaving only the patterned silicon oxide layer 242, the metal stamps 103 and the metal TSV contacts 246 on the upper surface 240 a of the wafer 240. The wafer 240 is then singulated at the locations indicated by dashed lines 248.

FIG. 8 illustrates a side plan view of a TSA eWLB assembly comprising a stack of TSA eWLB packages 310 and 320 mounted on a PCB 330. The TSA eWLB package 310 is fabricated by the process steps described above with reference to FIGS. lA-2E, except that package 310 includes only die 110 (it does not include die 111). The electrical contact pad 124 a disposed on the front face 110 a of the die 110 is electrically connected to a solder ball 127 a by electrical trace 122 a and TMV 123 a. The electrical trace 122 a is part of the redistribution layer 121 of package 310. Any electrical contact pad (not shown) disposed on the rear face 110 b of the die 110 is electrically connected to a solder ball 127 b by the metal stamp 103 a. The solder balls 127 a and 127 b are electrically connected to an electrical trace 122 b of package 320. The die 110 may be an optical-to-electrical (O/E) or an electrical-to-optical (E/O) die such as, for example, a VCSEL die, an LED die or a photodiode die.

The TSA eWLB package 320 includes a silicon die 340, which may be, for example, a receiver IC die, an LED driver die or a VCSEL die, depending on the type of die 110 that is used in package 110. The package 320 may be fabricated using the process described above with reference to FIGS. 7A-7E followed by the process described above with reference to FIGS. 2B-2E. The package 320 has two TMVs 123 b and 123 c that are connected on first ends to respective solder balls 127 c and 127 d and on second ends to electrical trace 122 c, which is connected to the electrical contact pad 124 b disposed on the front face 340 a of die 344. Electrical trace 122 b, which is connected to solder balls 127 a and 127 b, is connected to a contact pad 124 c disposed on the front face 340 a of die 340. The electrical traces 122 b and 122 c are part of the redistribution layer 121 of package 320.

The rear face 340 b of the die 340 is electrically connected to solder ball 127 e by metal stamp 103 b. A metal TSV contact 246 is also disposed on the rear face 340 b of die 340 and is connected to a solder ball 127 f and to a first end of a TSV 241. A second end of the TSV 241 is connected to an electrical trace 122 d, which is connected to an electrical contact pad 124 d disposed on the front face 340 a of die 340. The solder balls 127 c-127 f are in contact with electrical contacts 330 b-330 e, respectively, disposed on an upper surface 330 a of PCB 330.

Through all of these electrical connections between the PCB 330 and package 320 and between package 320 and package 310, electrical signals can be communicated between: the PCB 330 and the package 320; the package 320 and the package 310; and the PCB 330 and the package 310.

FIG. 9 illustrates a side plan view of a TSA eWLB assembly that is similar the the TSA eWLB assembly shown in FIG. 8 except that no TSVs are used in the assembly shown in FIG. 9. The TSA eWLB assembly shown in FIG. 9 comprises a stack of TSA eWLB packages 310 and 360 mounted on a PCB 370. The TSA eWLB package 310 shown in FIG. 9 is identical to the TSA eWLB package 310 shown in FIG. 8. In the assembly shown in FIG. 9, the packages 310 and 360 are positioned relative to one another such that the solder balls 127 a and 127 b are in contact with the TMVs 123 c and 123 b, respectively.

The TSA eWLB package 360 includes a silicon die 380, which may be, for example, a receiver IC die, an LED driver die or a VCSEL die, depending on the type of die 110 that is used in package 110. The package 360 may be fabricated using the same process steps that are used to fabricate package 110 since package 360 has no TSVs. The package 360 has two TMVs 123 b and 123 c that are connected on first ends to respective solder balls 127 c and 127 d and on second ends to solder balls 127 b and 127 a, respectively.

The rear face 380 b of the die 380 is electrically connected to solder balls 127 e-127 h by metal stamps 103 b-103 e, respectively. All of the solder balls 127 c-127 h are in contact with electrical wiring 371 disposed on the upper surface 370 a of the PCB 370. Through all of these electrical connections between the PCB 370 and the packages 310 and 360, electrical signals can be communicated between: the PCB 370 and the package 310; the package 310 and the package 360; and the PCB 370 and the package 360.

It can be seen from the description of the illustrative embodiments provided above that the TSA eWLB package of the invention provides the advantage of allowing electrical contact pads disposed on the front and/or the rear faces of the IC dies to be easily accessed. In particular, the invention allows wafer-level processes to be used to create the electrically-conductive pathways that are needed in the packages in order to electrically connect the electrical contact pads of the IC dies with the electrical contacts of the PCB. Consequently, the electrical connections can be made with greater precision, at reduced manufacturing costs and with higher manufacturing yield.

It should be noted that the invention has been described with reference to a few illustrative embodiments for the purpose of demonstrating the principles and concepts of the invention. It will be understood by persons of skill in the art, in view of the description provided herein, that the invention is not limited to these illustrative embodiments. For example, the invention has been described with respect to examples of particular configurations of TSA eWLB packages made using methods of the invention, but the invention is not limited with respect to the particular configurations of the TSA eWLB packages. The invention also is not limited to the particular sequences of process steps described above with reference to the figures. Persons of skill in the art will understand that many variations can be made to the illustrative embodiments without deviating from the scope of the invention. 

What is claimed is:
 1. A chip package comprising: a mold having a front side and a rear side; a first set of electrical traces disposed on the front side of the mold; a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the first set of electrical traces, the front face of the IC die having a first electrical contact pad disposed thereon that is in contact with the first set of electrical traces; a rear-side metallization exposed on a rear face of the first IC die, wherein a portion of the rear-side metallization is exposed through the rear side of the mold; and a first solder ball disposed on the exposed portion of the rear-side metallization.
 2. The chip package of claim 1, further comprising: a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the first set of electrical traces; a second rear-side metallization disposed on a rear face of the second IC die, wherein a portion of the second rear-side metallization is exposed through the rear side of the mold; and a second solder ball disposed on the exposed portion of the second rear-side metallization.
 3. The chip package of claim 2, wherein the first and second IC dies are of different types.
 4. The chip package of claim 2, wherein the second IC die has electrical contact pads disposed on the front faces thereof, and wherein the electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by the first set of electrical traces.
 5. The chip package of claim 2, further comprising: a first via formed in the mold that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first via is located on the rear side of the mold and a second end of the first via is located on the front side of the mold; and at least a third solder ball disposed on the first end of the first via.
 6. The chip package of claim 5, wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a second set of electrical traces.
 7. The chip package of claim 2, wherein the second IC die is a silicon die, and wherein the chip package further comprises: a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die; a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and at least a third solder ball disposed on the first TSV electrical contact.
 8. The chip package of claim 7, wherein the second end of the first TSV is electrically connected to a second electrical contact pad disposed on the front face of the second IC die by an electrical trace in the first set of electrical traces.
 9. The chip package of claim 1, further comprising: an optical element located adjacent the front face of the first IC die.
 10. The chip package of claim 9, wherein the optical element is at least one of a refractive lens, a Fresnel lens, and a holographic element.
 11. A two-sided-access extended, or embedded, wafer-level ball grid array (TSA eWLB) assembly comprising: a TSA eWLB package comprising: a mold having a front side and a rear side, a redistribution layer disposed on front side of the mold, the redistribution layer including layers of metal patterned to form electrical traces, at least a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the redistribution layer, the front face of the first IC having at least a first electrical contact pad disposed thereon that is in contact with the redistribution layer, a metal pattern disposed on a rear face of the first IC die and exposed through the rear side of the mold, the rear face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the metal pattern, and a first solder ball disposed on the exposed portion of the metal pattern; and a printed circuit board (PCB) having an upper surface and a lower surface, the upper surface having electrical contacts disposed thereon, the TSA eWLB package being mounted on the upper surface of the PCB such that said at least a first solder ball of the TSA eWLB package is in contact with the one of the electrical contacts disposed on the upper surface of the PCB.
 12. The TSA eWLB assembly of claim 11, wherein the TSA eWLB package further comprises: a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the redistribution layer; a second metal pattern disposed on a rear face of the second IC die, wherein a portion of the second metal pattern is exposed through the rear side of the mold; and a second solder ball disposed on the exposed portion of the second metal pattern, and wherein the second solder ball is in contact with one of the electrical contacts disposed on the upper surface of the PCB.
 13. The TSA eWLB assembly of claim 12, wherein the first and second IC dies are of different types.
 14. The TSA eWLB assembly of claim 12, wherein the second IC die has at least a first electrical contact pad disposed on the front face thereof, and wherein the first electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by a first electrical trace of the redistribution layer.
 15. The TSA eWLB assembly of claim 12, wherein the TSA eWLB package further comprises: a first thru-mold via (TMV) formed in the mold, the first TMV comprising a hole that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first TMV is located on the rear side of the mold and a second end of the first TMV is located on the front side of the mold; and a third solder ball disposed on the first end of the first TMV, the third solder ball being in contact with one of the electrical contacts disposed on the upper surface of the PCB.
 16. The TSA eWLB assembly of claim 15, wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a second electrical trace of the redistribution layer.
 17. The TSA eWLB assembly of claim 12, wherein the second IC die is a silicon die, and wherein the TSA eWLB package further comprises: at least a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die; a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and a third solder ball disposed on the first TSV electrical contact, the third solder ball being in contact with one of the electrical contacts disposed on the upper surface of the PCB.
 18. The TSA eWLB assembly of claim 17, wherein the second end of the first TSV is electrically connected to a second electrical contact pad disposed on the front face of the second IC die by a second electrical trace of the redistribution layer.
 19. The TSA eWLB assembly of claim 12, wherein the first IC die is an electrical-to-optical converter and the second IC die is an optical-to-electrical converter, and wherein the assembly further comprises: a cap secured to the front side of the mold, the cap having first and second optical pathways formed therein, the first and second optical pathways being located above the first and second IC dies, respectively, the first optical pathway directing light emitted by the first IC die in a direction that is away from the first IC die and generally normal to the front face of the first IC die, the second optical pathway directing light that falls onto the assembly and onto the second optical pathway in a direction that is toward the second IC die and generally normal to the front face of the second IC die. 